The present invention generally relates to semiconductor devices and methods of producing semiconductor devices, and more particularly to a semiconductor device having a metal oxide semiconductor (MOS) transistor provided on a substrate and a method of producing such a semiconductor device having high integration density and improved characteristics.
Recently, in order to further improve the integration density of integrated circuits (ICs), there is a demand to change a P-channel MOS transistor from a buried channel type into a surface channel type. For this reason, it is necessary to form a gate electrode from a P-type polysilicon instead of an N-type polysilicon. Ion implantation and thermal diffusion are carried out to form the gate electrode into the P-type, but there is a problem in that the P-type impurities and particularly boron (B) easily penetrate the gate electrode and reach the channel portion. The above described problem is caused by the large R.sub.p of the P-type impurities such as B and the fact that the diffusion easily occurs within silicon dioxide (SiO.sub.2), where R.sub.1 denotes a depth of the ion implantation from a surface.
As one method of overcoming the above described problem, there is a known method of forming a gate insulator layer of the P-channel MOS transistor from a composite layer of SiO.sub.2 and silicon nitride (Si.sub.3 N.sub.4) layers in order to suppress the diffusion of the P-type impurities into the channel portion, instead of forming the gate insulator layer of the P-channel MOS transistor solely from a SiO.sub.2 layer. The P-type impurities are much less likely to diffuse into the Si.sub.3 N.sub.4 layer when compared to the SiO.sub.2 layer, and the Si.sub.3 N.sub.4 acts as a stopper with respect to the impurity diffusion.
A conventional method of producing a semiconductor device will now be described with reference to FIGS. 1A through 1F.
In FIG. 1F, the completed semiconductor device includes a silicon (Si) substrate 31, a SiO.sub.2 field oxide layer 32, a P-channel MOS transistor region 33 in which a P-channel MOS transistor is formed, and an N-channel MOS transistor region 34 in which an N-channel MOS transistor is formed. An N-type well 35 is formed in the P-channel MOS transistor region 33, and a P-type well 36 is formed in the N-channel MOS transistor region 34. A silicon oxide layer 37 is made of SiO.sub.2 or the like, a silicon nitride layer 38 is made of Si.sub.3 N.sub.4 or the like, and a silicon oxide layer 39 is made of SiO.sub.2 or the like. A gate insulator layer 40 is made up of the silicon oxide layers 37 and 29 and the silicon nitride layer 38. A gate insulator layer 41 is made of SiO.sub.2 or the like, and a polysilicon layer 42 is provided for forming a gate electrode. A gate electrode 43 is formed in the P-channel MOS transistor region 33, and a gate electrode 44 is formed in the N-channel MOS transistor region 34. A substrate diffusion layer 45 is formed in the P-channel MOS transistor region 33 and functions as a source/drain diffusion layer. A substrate diffusion layer 46 is formed in the N-channel MOS transistor region 34 and functions as a source/drain diffusion layer. An interlayer insulator layer 47 is made of phospho-silicate glass (PSG) or the like. A contact hole 48 is formed in the interlayer insulator layer 47, and an interconnection layer 49 is made of aluminum (Al) or the like.
The semiconductor device shown in FIG. 1F is produced as follows.
First, as shown in FIG. 1A, the substrate 31 is selectively thermally oxidized by local oxidation of silicon (LOCOS), so as to form the field oxide layer 32 as an isolation region and to form the P-channel MOS transistor region 33 and the N-channel MOS transistor region 34 as active regions. Ion implantation is used to implant N-type impurities in a region where a P-channel MOS transistor is formed and to implant P-type impurities in a region where an N-channel MOS transistor is formed, and the N-type well 35 and the P-type well 36 are formed by a thermal process. Then, the silicon oxide layer 37 which is made of SiO.sub.2 is formed on the entire surface by a thermal oxidation, for example. Si.sub.3 N.sub.4 is accumulated on the silicon oxide layer 37 by a chemical vapor deposition (CVD), for example, so as to form the silicon nitride layer 38. Thereafter, the silicon nitride layer 38 is oxidized by a thermal oxidation, for example, so as to form on the surface of the silicon nitride layer 38 the silicon oxide layer 39 which is made of SiO.sub.2.
Next, as shown in FIG. 1B, the silicon oxide layer 39, the silicon nitride layer 38 and the silicon oxide layer 37 of the N-channel MOS transistor region 34 are selectively etched by a reactive ion etching (RIE), for example. Hence, the gate insulator layer 40 made up of the silicon oxide layer 37, the silicon nitride layer 38 and the silicon oxide layer 39 is formed in the P-channel MOS transistor region 33 while the substrate 31 is exposed in the N-channel MOS transistor region 34.
Then, as shown in FIG. 1C, the gate insulator layer 41 made of SiO.sub.2 is formed in the N-channel MOS transistor region 34 by a thermal oxidation, for example. In this state, the silicon nitride layer 38 is further oxidized and increases the thickness of the silicon oxide layer 39.
Next, as shown in FIG. 1D, a polysilicon layer 42 is accumulated to cover the entire surface of the P-channel MOS transistor region 33 and the N-channel MOS transistor region 34 by a CVD, for example. This polysilicon layer 42 is used for the gate electrode and the resistivity thereof is decreased by impurity doping.
Thereafter, as shown in FIG. 1E, the polysilicon layer 42 and the gate insulator layers 40 and 41 of the respective P-channel MOS transistor region 3 and the N-channel MOS transistor region 34 are selectively etched by a RIE, for example, so as to form the gate electrode 43 in the P-channel MOS transistor region 33 and the gate electrode 44 in the N-channel MOS transistor region 34. In this state, the substrate 31 the N-type well or the P-type well 36) is exposed in the P-channel MOS transistor region 33 and the N-type MOS transistor region 34. The gate electrode 43 of the P-channel MOS transistor region 33 and the gate electrode 44 of the N-channel MOS transistor region 34 may be formed independently. For example, the gate electrode 44 of the N-channel MOS transistor region 34 may be formed after the gate electrode 43 of the P-channel MOS transistor region 33 is formed.
In addition, it is possible to leave the silicon oxide layer 37 or the gate insulator layer 41 by etching the gate electrode using an etchant which has a high selectivity.
Next, the substrate diffusion layer 45 which becomes the source/drain diffusion layer is formed in the P-channel MOS transistor region 33, and the substrate diffusion layer 46 which becomes the source/drain diffusion layer is formed in the N-channel MOS transistor region 34. In addition, the interlayer insulator layer 47 which is made up of SiO.sub.2 and PSG is formed on the entire surface to cover the P-channel MOS transistor region 33 and the N-channel MOS transistor region 34. The contact holes 48 are formed in the interlayer insulator layer 47 and the substrate diffusion layers 45 and 46 so as to expose the gate electrodes 43 and 44. Thereafter, the Al interconnection layer 49 is formed to make contact with the substrate diffusion layers 45 and 46 and the gate electrodes 43 and 44 via the contact holes 48. As a result, the completed semiconductor device shown in FIG. 1F is obtained.
However, according to the conventional method, there is a problem in that it is impossible to independently form the gate insulator layers 40 and 41 of the respective P-channel MOS transistor and the N-channel MOS transistor. Furthermore, there are problems in that the thicknesses of the gate insulator layers 40 and 41 cannot be controlled to desired values and it is impossible to optimize the threshold voltage V.sub.th or the like of the MOS transistors.
The thicknesses of the gate insulator layers 40 and 41 cannot be controlled to the desired values for the following reasons. That is, when the silicon nitride layer 38 which is provided at the P-channel MOS transistor region 33 to act as a diffusion stopper is oxidized at a high temperature of 1000.degree. C., for example, the thickness of the SiO.sub.2 gate insulator layer 41 in the N-channel MOS transistor region 34 may become greater than the desired value. On the other hand, when an attempt is made to control the thickness of the gate insulator layer 41 in the N-channel MOS transistor region 34 to the desired value, a SiO.sub.2 layer of a sufficient thickness cannot be formed on the silicon nitride layer 38 in the P-channel MOS transistor region 33 and the thickness of the silicon oxide layer 39 becomes less than the desired value, thereby making the withstand voltage poor. The oxidation of the silicon nitride layer 38 is carried out at the high temperature in order to stop the leak current caused by the trap of the silicon nitride layer and to prevent the initial short-circuit by mutually compensating for the pin holes existing in each layer of the multi-layer insulator layer. In addition, the oxidation of the silicon nitride layer 38 is also carried out to increase the thickness of the silicon oxide layer 39 and improve the withstand voltage, so that the deterioration caused by hot carriers is suppressed and the life time of the device as a result is prolonged.